An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation

This paper describes a novel on-chip digital aging sensor circuit capable of detecting MOS transistors wearout due to negative-bias temperature instability (NBTI). The proposed aging sensor circuit enables us to identify the Vt h shift of a pMOS transistor only from the sensing outputs without building simulation models or complex calibration procedures. To achieve this, the proposed circuit monitors the leakage-current based charge accumulation speed that is affected by a stressed pMOS power switch. We designed and implemented a test chip in a 65nm FDSOI CMOS technology. By operating the fabricated test chip at an ultra-low voltage (i.e. 0.3 V), we observed a clear linear relationship between the logarithm of the charge accumulation time and the reciprocal of the temperature, which is indicated in derived analytical expressions. From the slope value of the linear relationship, the rate of increase in V t h due to stress was successfully obtained. We also demonstrate that the proposed aging sensor circuit can detect aging at actual use at a nominal voltage.