An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Tadashi Maeda; Keiichi Numata; Masahiro Fujii; Masatoshi Tokushima; Shigeki Wada; Muneo Fukaishi; Masaoki Ishikawa

doi:10.1109/4.535426

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

本文言語	English
ページ（範囲）	1361-1363
ページ数	3
ジャーナル	IEEE Journal of Solid-State Circuits
巻	31
号	9
DOI	https://doi.org/10.1109/4.535426
出版ステータス	Published - 1996 9月 1
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.535426

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AU - Tokushima, Masatoshi

AU - Wada, Shigeki

AU - Fukaishi, Muneo

AU - Ishikawa, Masaoki

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AB - The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

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An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

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