TY - GEN
T1 - Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP
AU - Takatani, Hiroki
AU - Tanaka, Yosuke
AU - Fujita, Haruya
AU - Oizono, Yoshiaki
AU - Nabeshima, Yoshitaka
AU - Sudo, Toshio
AU - Sakai, Atsushi
AU - Uchiyama, Shiro
AU - Ikeda, Hiroaki
PY - 2012/12/1
Y1 - 2012/12/1
N2 - The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.
AB - The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.
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U2 - 10.1109/EDAPS.2012.6469419
DO - 10.1109/EDAPS.2012.6469419
M3 - Conference contribution
AN - SCOPUS:84875512613
SN - 9781467314435
T3 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
SP - 185
EP - 188
BT - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
T2 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Y2 - 9 December 2012 through 11 December 2012
ER -