This paper presents the analysis and PCB design of a class D inverter for wireless power transfer systems operating at 13.56 MHz. The effects of parasitic inductance on the switching performance of MOSFETs, transfer efficiency of WPT systems, and power loss are analyzed. At high frequencies, the print circuit board (PCB) design is very critical because it control the parasitic elements on the circuit. This study proposes an improved PCB design that can provide a 23.4% decrease in parasitic inductance over the conventional PCB design.
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