抄録
Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 37-41 |
| ページ数 | 5 |
| ジャーナル | IEEE Transactions on Electron Devices |
| 巻 | 49 |
| 号 | 1 |
| DOI | |
| 出版ステータス | Published - 2002 1月 1 |
ASJC Scopus subject areas
- 電子材料、光学材料、および磁性材料
- 電子工学および電気工学