TY - JOUR
T1 - Analysis of the operating-speed and power consumption of GaAs DCFL D-type flip-flops
AU - Maeda, T.
PY - 1997/6
Y1 - 1997/6
N2 - The article describes, in terms of steady-state sinusoidal analysis, simple analytical expressions for the operating speed and power consumption of DCFL D-type flip-flops. The maximum operating speed fOPmax is limited to fT sin{π/(nG + 1)}/2nFO, where fT is the cut-off frequency, nG is the number of critical path gates, and nFO is the fan-out number. In contrast, the influence of maximum frequency of oscillation fmax on fOPmax is small compared with that for fT, but an FET with a higher fmax can reduce the power consumption. These analytical results agree well with the experimental results.
AB - The article describes, in terms of steady-state sinusoidal analysis, simple analytical expressions for the operating speed and power consumption of DCFL D-type flip-flops. The maximum operating speed fOPmax is limited to fT sin{π/(nG + 1)}/2nFO, where fT is the cut-off frequency, nG is the number of critical path gates, and nFO is the fan-out number. In contrast, the influence of maximum frequency of oscillation fmax on fOPmax is small compared with that for fT, but an FET with a higher fmax can reduce the power consumption. These analytical results agree well with the experimental results.
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U2 - 10.1016/S0038-1101(97)00049-X
DO - 10.1016/S0038-1101(97)00049-X
M3 - Article
AN - SCOPUS:0031170014
SN - 0038-1101
VL - 41
SP - 807
EP - 811
JO - Solid-State Electronics
JF - Solid-State Electronics
IS - 6
ER -