Cache controller design on ultra low leakage embedded processors

Zhao Lei, Hui Xu, Naomi Seki, Saito Yoshiki, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano

研究成果: Conference article査読


A leakage-efficient cache controller design targeted on ultra low power embedded processors is proposed. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the fine-grained run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control policies are proposed to assure the leakage reduction effect; and to eliminate the impact of wake-up process, a latency cancellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.

ジャーナルLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
5455 LNCS
出版ステータスPublished - 2009 4月 6
イベント22nd International Conference on Architecture of Computing Systems - ARCS 2009 - Delft, Netherlands
継続期間: 2009 3月 102009 3月 13

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • コンピュータ サイエンス(全般)


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