抄録
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.
| 本文言語 | English |
|---|---|
| ページ | 307-312 |
| ページ数 | 6 |
| 出版ステータス | Published - 1998 12月 1 |
| 外部発表 | はい |
| イベント | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn 継続期間: 1998 2月 10 → 1998 2月 13 |
Other
| Other | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
|---|---|
| City | Yokohama, Jpn |
| Period | 98/2/10 → 98/2/13 |
ASJC Scopus subject areas
- コンピュータ サイエンスの応用
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学