This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.
|出版ステータス||Published - 1995|
|イベント||Proceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA|
継続期間: 1995 4月 23 → 1995 4月 26
|Other||Proceedings of the 1995 International Symposium on Low Power Design|
|City||Dana Point, CA, USA|
|Period||95/4/23 → 95/4/26|
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