TY - GEN
T1 - Datapath generator based on gate-level symbolic layout
AU - Matsumoto, Nobu
AU - Watanabe, Yoko
AU - Usami, Kimiyoshi
AU - Sugeno, Yukio
AU - Hatada, Hiroshi
AU - Mori, Shojiro
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 1990
Y1 - 1990
N2 - A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21K-transistor data-path whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath, was generated using 1-μm CMOS technology.
AB - A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21K-transistor data-path whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath, was generated using 1-μm CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=0025550664&partnerID=8YFLogxK
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U2 - 10.1145/123186.123314
DO - 10.1145/123186.123314
M3 - Conference contribution
AN - SCOPUS:0025550664
SN - 081869650X
T3 - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
SP - 388
EP - 393
BT - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
PB - Publ by IEEE
T2 - 27th ACM/IEEE Design Automation Conference
Y2 - 24 June 1990 through 28 June 1990
ER -