TY - GEN
T1 - Delay modeling and static timing analysis for MTCMOS circuits
AU - Ohkubo, Naoaki
AU - Usami, Kimiyoshi
PY - 2006/9/19
Y1 - 2006/9/19
N2 - One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.
AB - One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.
KW - Delay
KW - Interpolation
KW - Leakage power
KW - MTCMOS
KW - Selective-MT
KW - Static timing analysis
UR - http://www.scopus.com/inward/record.url?scp=33748588117&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748588117&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33748588117
SN - 0780394518
SN - 9780780394513
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 570
EP - 575
BT - Proceedings of the ASP-DAC 2006
T2 - ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Y2 - 24 January 2006 through 27 January 2006
ER -