Design and evaluation of fine-grained power-gating for embedded microprocessors

Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura

研究成果: Conference contribution

17 被引用数 (Scopus)


Power-performance efficiency is still remaining a primary concern for microprocessor designers. One of the sources of power inefficiency for recent LSI chips is increasing leakage power consumption. Power-gating is a well known technique to reduce leakage power consumption by switching off the power supply to idle logic blocks. Recently, fine-grained power-gating is emerged as a technique to minimize leakage current during the active processor cycles by switching on and off a logic blocks in much finer temporal/spatial granularity. Though fine-grained power-gating is useful, a comprehensive evaluation and analysis has not been conducted on a real LSI chips. In this paper, we evaluate fine-grained run-time power-gating for microprocessors' functional units using a real embedded microprocessor. We also introduce an architecture and compiler co-operative power-gating scheme which mitigates negative power reduction caused by the energy overhead associated with finegrained power-gating. The experimental results with a fabricated core shows that a hardware-based scheme saves power consumption of functional units by 44% and hardware compiler co-operative scheme further improves power efficiency by 5.9% when core temperature is 25 ̊C.

ホスト出版物のタイトルProceedings - Design, Automation and Test in Europe, DATE 2014
出版社Institute of Electrical and Electronics Engineers Inc.
出版ステータスPublished - 2014
イベント17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
継続期間: 2014 3月 242014 3月 28


名前Proceedings -Design, Automation and Test in Europe, DATE


Conference17th Design, Automation and Test in Europe, DATE 2014

ASJC Scopus subject areas

  • 工学(全般)


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