Design and implementation fine-grained power gating on microprocessor functional units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano

研究成果: Article査読

4 被引用数 (Scopus)


In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip . Geyser-1 has been implemented with Fujitsu's 65 nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25°C and 23% at 80°C.

ジャーナルIPSJ Transactions on System LSI Design Methodology
出版ステータスPublished - 2011

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学


「Design and implementation fine-grained power gating on microprocessor functional units」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。