Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida; Kimiyoshi Usami

doi:10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida, Kimiyoshi Usami

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

本文言語	English
ホスト出版物のタイトル	Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
編集者	Androula G. Nassiopoulou, Panagiotis Sarafis
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	43-46
ページ数	4
ISBN（電子版）	9781509053131
DOI	https://doi.org/10.1109/ULIS.2017.7962596
出版ステータス	Published - 2017 6月 29
イベント	2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece 継続期間: 2017 4月 3 → 2017 4月 5

出版物シリーズ

名前	Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

Other

Other	2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
国/地域	Greece
City	Athens
Period	17/4/3 → 17/4/5

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
器械工学
電子工学および電気工学

文献へのアクセス

10.1109/ULIS.2017.7962596

他のファイルとリンク

!!Link to publication in Scopus

フィンガープリント

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引用スタイル

Yoshida, Y., & Usami, K. (2017). Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In A. G. Nassiopoulou, & P. Sarafis (Eds.), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 43-46). [7962596] (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. / Yoshida, Yusuke; Usami, Kimiyoshi.
Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. ed. / Androula G. Nassiopoulou; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. p. 43-46 7962596 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

研究成果: Conference contribution

Yoshida, Y & Usami, K 2017, Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. in AG Nassiopoulou & P Sarafis (eds), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings., 7962596, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 43-46, 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Athens, Greece, 17/4/3. https://doi.org/10.1109/ULIS.2017.7962596

Yoshida Y, Usami K. Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In Nassiopoulou AG, Sarafis P, editors, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 43-46. 7962596. (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). doi: 10.1109/ULIS.2017.7962596

Yoshida, Yusuke ; Usami, Kimiyoshi. / Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. editor / Androula G. Nassiopoulou ; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 43-46 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

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abstract = "This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.",

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