Design of a 32bit microprocessor, TX1

Takeji Tokumaru; Eiji Masuda; Chikahiro Hori; Kimiyoshi Usami; Misao Miyata; Jun Iwamura

Design of a 32bit microprocessor, TX1

Takeji Tokumaru, Eiji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura

研究成果: Paper › 査読

抄録

TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.

本文言語	English
ページ	33-34
ページ数	2
出版ステータス	Published - 1988 12月 1
外部発表	はい
イベント	1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan 継続期間: 1988 8月 22 → 1988 8月 24

Other

Other	1988 Symposium on VLSI Circuits - Digest of Technical Papers
City	Tokyo, Japan
Period	88/8/22 → 88/8/24

ASJC Scopus subject areas

工学（全般）

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引用スタイル

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AU - Tokumaru, Takeji

AU - Masuda, Eiji

AU - Hori, Chikahiro

AU - Usami, Kimiyoshi

AU - Miyata, Misao

AU - Iwamura, Jun

PY - 1988/12/1

Y1 - 1988/12/1

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AB - TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.

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T2 - 1988 Symposium on VLSI Circuits - Digest of Technical Papers

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ER -

Design of a 32bit microprocessor, TX1

抄録

Other

ASJC Scopus subject areas

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