Design optimization of wiring substrate in a CMOS-based multichip module

Toshio Sudo, Naohiko Hirano, Katsuto Kato, Youichi Hiruta, Yumi Fuchida

研究成果: Conference contribution

1 被引用数 (Scopus)


Both line resistance and RC values for MCMs (multichip modules) have been found to be located in the medium position between that of LSIs and PWBs (printed wiring boards). This leads to a tradeoff between process design and output buffer design. The effects of line resistance on the electrical performance in CMOS-based MCMs are described. Switching noise, ringing noise, interconnect delay, and crosstalk noise in the line resistance range of a thin-film wiring substrate are discussed. Signal line resistance works as a damping resistor both for switching noise and for signal ringing noise. There are optimum damping conditions. The chip-to-chip delay was not substantially influenced by the line resistance as long as the line length was kept short. The line resistance, i.e., the characteristic impedance, as well as the line resistance has an important role in determining the signal propagation properties whether it behaves like an RC delay or it is in the region of the time of flight. The design of the wiring substrate must be optimized for CMOS buffer drivability to have good electrical properties and not to impose excessive requirements on thin-film process technology.

ホスト出版物のタイトルProceedings - Electronic Components Conference
出版社Publ by IEEE
出版ステータスPublished - 1992 1月 1
イベントProceedings of the 42nd Electronic Components and Technology Conference - San Diego, CA, USA
継続期間: 1992 5月 181992 5月 20


名前Proceedings - Electronic Components Conference


OtherProceedings of the 42nd Electronic Components and Technology Conference
CitySan Diego, CA, USA

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学


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