TY - GEN
T1 - Digital embedded memory scheme using voltage scaling and body bias separation for low-power system
AU - Yoshida, Yusuke
AU - Usami, Kimiyoshi
AU - Amano, Hideharu
PY - 2018/5/29
Y1 - 2018/5/29
N2 - Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.
AB - Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.
KW - Body bias control
KW - Low-power
KW - Silicon-on-Thin-BOX (SOTB)
KW - Standard cell memory
KW - Ultra-low voltage
UR - http://www.scopus.com/inward/record.url?scp=85048867562&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048867562&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2017.8368840
DO - 10.1109/ISOCC.2017.8368840
M3 - Conference contribution
AN - SCOPUS:85048867562
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 148
EP - 149
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International SoC Design Conference, ISOCC 2017
Y2 - 5 November 2017 through 8 November 2017
ER -