Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

This paper describes a dynamic V_DD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower V_DD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic V_DD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.