GaAs buffering circuit ISI for ultra-fast data processing systems

T. Maeda; Y. Miyatake; Y. Tomonoh; S. Asai; M. Ishikawa; K. Nakaizumi; Y. Ohno; N. Ohno; T. Furutsuka

GaAs buffering circuit ISI for ultra-fast data processing systems

T. Maeda, Y. Miyatake, Y. Tomonoh, S. Asai, M. Ishikawa, K. Nakaizumi, Y. Ohno, N. Ohno, T. Furutsuka

研究成果: Paper › 査読

抄録

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

本文言語	English
ページ	139-142
ページ数	4
出版ステータス	Published - 1988 12月 1
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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Link to publication in Scopus

引用スタイル

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author = "T. Maeda and Y. Miyatake and Y. Tomonoh and S. Asai and M. Ishikawa and K. Nakaizumi and Y. Ohno and N. Ohno and T. Furutsuka",

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AU - Maeda, T.

AU - Miyatake, Y.

AU - Tomonoh, Y.

AU - Asai, S.

AU - Ishikawa, M.

AU - Nakaizumi, K.

AU - Ohno, Y.

AU - Ohno, N.

AU - Furutsuka, T.

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

AB - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

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EP - 142

ER -

GaAs buffering circuit ISI for ultra-fast data processing systems

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ASJC Scopus subject areas

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