TY - JOUR
T1 - GaAs Multichip Module for a Parallel Processing System
AU - Miyagi, Takeshi
AU - Itoh, Kenji
AU - Kimijima, Susumu
AU - Sudo, Toshio
N1 - Funding Information:
Manuscript received February 9, 1990; revised June 22, 1990. This work was performed as a part of “Research and Development of Scientific Computing System,” sponsored by the New Energy and Industrial Technology Development Organization. This paper was presented at the 40th Electronic Components and Technology Conference, Las Vegas, NV, May 21-23, 1990.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 1990/12
Y1 - 1990/12
N2 - A high-speed data transfer network for a parallel processing system has been developed by multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PU's) has been achieved in a module by 8-b slice GaAs bus logic (BL) LSI's, which operate at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSI's in a 3 by 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin film termination resistors are made of Ni/Cr in the substrate to prevent reflections. Heat generated from the module, which has a total of 90-W power dissipation, is transferred through four heat-pipes with fins to the ambient by forced air cooling at below 2 m/s. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by 4 stacked modules of 48 GaAs BL's.
AB - A high-speed data transfer network for a parallel processing system has been developed by multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PU's) has been achieved in a module by 8-b slice GaAs bus logic (BL) LSI's, which operate at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSI's in a 3 by 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin film termination resistors are made of Ni/Cr in the substrate to prevent reflections. Heat generated from the module, which has a total of 90-W power dissipation, is transferred through four heat-pipes with fins to the ambient by forced air cooling at below 2 m/s. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by 4 stacked modules of 48 GaAs BL's.
UR - http://www.scopus.com/inward/record.url?scp=0025557040&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0025557040&partnerID=8YFLogxK
U2 - 10.1109/33.62526
DO - 10.1109/33.62526
M3 - Article
AN - SCOPUS:0025557040
SN - 0148-6411
VL - 13
SP - 828
EP - 832
JO - IEEE Transactions on Components, Hybrids, and Manufacturing Technology
JF - IEEE Transactions on Components, Hybrids, and Manufacturing Technology
IS - 4
ER -