Highly integrated 3-D MMIC technology being applied to novel masterslice GaAs- and Si-MMIC's

Tsuneo Tokumitsu; Makoto Hirano; Kimiyoshi Yamasaki; Chikara Yamaguchi; Masayoshi Aikawa

Highly integrated 3-D MMIC technology being applied to novel masterslice GaAs- and Si-MMIC's

Tsuneo Tokumitsu, Makoto Hirano, Kimiyoshi Yamasaki, Chikara Yamaguchi, Masayoshi Aikawa

研究成果: Paper › 査読

抄録

A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.

本文言語	English
ページ	151-154
ページ数	4
出版ステータス	Published - 1996 12月 1
イベント	Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Orlando, FL, USA 継続期間: 1996 11月 3 → 1996 11月 6

Other

Other	Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
City	Orlando, FL, USA
Period	96/11/3 → 96/11/6

ASJC Scopus subject areas

電子工学および電気工学

他のファイルとリンク

引用スタイル

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title = "Highly integrated 3-D MMIC technology being applied to novel masterslice GaAs- and Si-MMIC's",

abstract = "A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.",

author = "Tsuneo Tokumitsu and Makoto Hirano and Kimiyoshi Yamasaki and Chikara Yamaguchi and Masayoshi Aikawa",

year = "1996",

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AU - Tokumitsu, Tsuneo

AU - Hirano, Makoto

AU - Yamasaki, Kimiyoshi

AU - Yamaguchi, Chikara

AU - Aikawa, Masayoshi

PY - 1996/12/1

Y1 - 1996/12/1

N2 - A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.

AB - A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.

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M3 - Paper

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T2 - Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium

Y2 - 3 November 1996 through 6 November 1996

ER -

Highly integrated 3-D MMIC technology being applied to novel masterslice GaAs- and Si-MMIC's

抄録

Other

ASJC Scopus subject areas

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