TY - GEN
T1 - Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system
AU - Kikuchi, Katsuya
AU - Takemura, Koichi
AU - Ueda, Chihiro
AU - Shimada, Osamu
AU - Gomyo, Toshio
AU - Takeuchi, Yukiharu
AU - Okubo, Toshikazu
AU - Baba, Kazuhiro
AU - Aoyagi, Masahiro
AU - Sudo, Toshio
AU - Otsuka, Kanji
PY - 2009
Y1 - 2009
N2 - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.
AB - We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.
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U2 - 10.1109/EPEPS.2009.5338487
DO - 10.1109/EPEPS.2009.5338487
M3 - Conference contribution
AN - SCOPUS:74549125795
SN - 9781424444472
T3 - 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
SP - 25
EP - 28
BT - 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
T2 - 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Y2 - 19 October 2009 through 21 October 2009
ER -