Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida

研究成果: Article査読

43 被引用数 (Scopus)

抄録

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

本文言語English
ページ(範囲)375-382
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
41
2
DOI
出版ステータスPublished - 2006 2月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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