TY - GEN
T1 - Low-power design methodology and applications utilizing dual supply voltages
AU - Usami, Kimiyoshi
AU - Igarashi, Mutsunori
PY - 2000
Y1 - 2000
N2 - This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.
AB - This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.
UR - http://www.scopus.com/inward/record.url?scp=0010893420&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0010893420&partnerID=8YFLogxK
U2 - 10.1145/368434.368590
DO - 10.1145/368434.368590
M3 - Conference contribution
AN - SCOPUS:0010893420
SN - 0780359747
SN - 9780780359741
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 123
EP - 128
BT - Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
T2 - 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Y2 - 25 January 2000 through 28 January 2000
ER -