Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package,

Y.Hiruta Y.Hiruta, N.Hirano N.Hirano, T.Sudo T.Sudo, Toshio Sudo

研究成果: Article › 査読

本文言語	English
ジャーナル	VLSI Packaging Workshop Japan
出版ステータス	Published - 1992 12月 1

引用スタイル

@article{184e93411cf245bfa6d41bdaaba74765,

title = "Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package,",

author = "Y.Hiruta Y.Hiruta and N.Hirano N.Hirano and T.Sudo T.Sudo and Toshio Sudo",

year = "1992",

month = dec,

day = "1",

language = "English",

journal = "VLSI Packaging Workshop Japan",

}