TY - JOUR
T1 - Multi bit PWMDAC with multi delay inverter
AU - Kodama, Daichi
AU - Ioka, Eri
AU - Matsuya, Yasuyuki
PY - 2013
Y1 - 2013
N2 - The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.
AB - The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.
KW - Data weighted averaging
KW - Digital-to-analog converter
KW - Multi delay inverter
KW - Pulse width modulation
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U2 - 10.1541/ieejeiss.133.239
DO - 10.1541/ieejeiss.133.239
M3 - Article
AN - SCOPUS:84874156964
SN - 0385-4221
VL - 133
SP - 239
EP - 244
JO - IEEJ Transactions on Electronics, Information and Systems
JF - IEEJ Transactions on Electronics, Information and Systems
IS - 2
ER -