TY - JOUR
T1 - Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping
AU - Nakano, H.
AU - Takayanagi, H.
AU - Yonemoto, K.
AU - Horio, K.
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.
AB - Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.
KW - Current collapse
KW - Deep level
KW - Device simulation
KW - FET
KW - GaN
UR - http://www.scopus.com/inward/record.url?scp=30944453534&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=30944453534&partnerID=8YFLogxK
U2 - 10.1109/CSICS.2005.1531789
DO - 10.1109/CSICS.2005.1531789
M3 - Conference article
AN - SCOPUS:30944453534
SN - 1550-8781
SP - 141
EP - 144
JO - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
JF - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
M1 - H.2
T2 - 2005 IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
Y2 - 30 October 2005 through 2 November 2005
ER -