Numerical Simulation of GaAs MESFET's with a p-Buffer Layer on the Semi-Insulating Substrate Compensated by Deep Traps

Numerical simulation of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thicker p-buffer layer results in lower device current due to the formation of a steeper barrier at the channel-substrate interface. It is also shown that in a case with higher acceptor and trap densities in the substrate, the drain current becomes lower due to the decrease in the substrate current. This decrease in the substrate current occurs due to the formation of a negative space-charge layer in the substrate. It is concluded that using a thick p-buffer layer has the same effect as using a substrate with a high density of traps inasmuch as both of them lead to minimizing the short-channel effects in GaAs MESFET's.