TY - JOUR
T1 - Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations
AU - Usami, Kimiyoshi
AU - Yokoyama, Daiki
AU - Kamei, Aika
AU - Amano, Hideharu
AU - Suzuki, Kenta
AU - Hiraga, Keizo
AU - Bessho, Kazuhiro
N1 - Publisher Copyright:
© 1993-2012 IEEE.
PY - 2024/1/1
Y1 - 2024/1/1
N2 - Introducing a magnetic tunneling junction (MTJ) into a flip-flop enables nonvolatile power gating (PG) but large store energy to MTJ is a critical concern. We propose an optimized two-step store (TSS) control to first perform a short store with an optimal time for all nonvolatile flip-flops (NVFFs) and then perform a long store only at the failed ones for reducing the store energy. As the key technologies to realize this, we present a verify-and-retryable NVFF (VR-NVFF) circuit enabling the TSS control and an analytical expression for the optimal short-store time (Tshort_opt) minimizing the store energy. To examine the effectiveness of the optimized TSS control and the validity of analytically derived Tshortopt, we implemented the TSS control on a coarse-grained reconfigurable array (CGRA)-based accelerator chip and fabricated it in a 40-nm CMOS/MTJ hybrid process technology. Results demonstrated that analytical Tshortopt showed a good agreement with the measured value (within 8% difference) under process and temperature variations. The TSS control with Tshortopt reduced the store energy to 0.32× of that of the conventional long-store-only technique. The break-even time (BET), which is the minimum power-gating time to get the gain in energy savings, was shortened to 0.51 0.7× by the TSS control, achieving the BET of 50 923 μ s in the range of 0 °C 80 °C.
AB - Introducing a magnetic tunneling junction (MTJ) into a flip-flop enables nonvolatile power gating (PG) but large store energy to MTJ is a critical concern. We propose an optimized two-step store (TSS) control to first perform a short store with an optimal time for all nonvolatile flip-flops (NVFFs) and then perform a long store only at the failed ones for reducing the store energy. As the key technologies to realize this, we present a verify-and-retryable NVFF (VR-NVFF) circuit enabling the TSS control and an analytical expression for the optimal short-store time (Tshort_opt) minimizing the store energy. To examine the effectiveness of the optimized TSS control and the validity of analytically derived Tshortopt, we implemented the TSS control on a coarse-grained reconfigurable array (CGRA)-based accelerator chip and fabricated it in a 40-nm CMOS/MTJ hybrid process technology. Results demonstrated that analytical Tshortopt showed a good agreement with the measured value (within 8% difference) under process and temperature variations. The TSS control with Tshortopt reduced the store energy to 0.32× of that of the conventional long-store-only technique. The break-even time (BET), which is the minimum power-gating time to get the gain in energy savings, was shortened to 0.51 0.7× by the TSS control, achieving the BET of 50 923 μ s in the range of 0 °C 80 °C.
KW - Analytical expression
KW - energy minimization
KW - magnetic tunneling junction (MTJ)
KW - nonvolatile flip-flop (NVFF)
KW - power gating (PG)
KW - process variation
KW - store energy
KW - temperature variation
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U2 - 10.1109/TVLSI.2023.3318468
DO - 10.1109/TVLSI.2023.3318468
M3 - Article
AN - SCOPUS:85174845057
SN - 1063-8210
VL - 32
SP - 89
EP - 102
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
ER -