PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure

Power supply impedance and simultaneous switching output (SSO) noise for a 3D system-in-package (SiP) with a wide bus structure have been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, these 3 stacked chips were assembled on the organic package substrate, whose size was 26 mm by 26 mm. The 3D stacked SiP with a widebus structure was estimated to have large SSO noise compared with conventional memory devices with small number of I/O s. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.