Power integrity behavior for various packaging environments

Masahiro Terasaki, Sho Kiyosige, Wataru Ichimura, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Toshio Sudo

研究成果: Paper査読

2 被引用数 (Scopus)


Power integrity design has become a critical issue in digital electronic systems, as advanced CMOS LSIs operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed on-chip PDN properties. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions the critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip. Furthermore QFP and BGA are used for a package and the effect of anti-resonance and power supply noise control by the total impedance of a chip package board are verified from the difference in inductance.

出版ステータスPublished - 2013 1月 1
イベント2013 3rd IEEE CPMT Symposium Japan, ICSJ 2013 - Kyoto, Japan
継続期間: 2013 11月 112013 11月 13


Conference2013 3rd IEEE CPMT Symposium Japan, ICSJ 2013

ASJC Scopus subject areas

  • 電子工学および電気工学


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