TY - GEN
T1 - Power integrity improvement by controlling on-die PDN properties
AU - Sudo, Toshio
AU - Kiyoshige, Sho
AU - Ichimura, Wataru
AU - Terasaki, Masahiro
AU - Kobayashi, Ryota
AU - Kubo, Genki
AU - Otsuka, Hiroki
PY - 2013/12/1
Y1 - 2013/12/1
N2 - Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the power distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, three test chips were designed with different on-chip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
AB - Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the power distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, three test chips were designed with different on-chip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
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U2 - 10.1109/EDAPS.2013.6724453
DO - 10.1109/EDAPS.2013.6724453
M3 - Conference contribution
AN - SCOPUS:84894112623
SN - 9781479923113
T3 - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
SP - 44
EP - 47
BT - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
T2 - 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Y2 - 12 December 2013 through 15 December 2013
ER -