Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages

Y. Umahashi, Y. Kambayashi, M. Kato, Y. Hasegawa, H. Amano, K. Usami

研究成果: Article › 査読

本文言語	English
ページ（範囲）	213-216
ジャーナル	The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)
出版ステータス	Published - 2008 7月 8

引用スタイル

@article{a6a3b744c31c4b4799fb3bbd2e1a56e7,

title = "Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages",

author = "Y. Umahashi and Y. Kambayashi and M. Kato and Y. Hasegawa and H. Amano and K. Usami",

year = "2008",

month = jul,

day = "8",

language = "English",

pages = "213--216",

journal = "The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)",

}

TY - JOUR

T1 - Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages

AU - Umahashi, Y.

AU - Kambayashi, Y.

AU - Kato, M.

AU - Hasegawa, Y.

AU - Amano, H.

AU - Usami, K.

PY - 2008/7/8

Y1 - 2008/7/8

M3 - Article

SP - 213

EP - 216

JO - The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)

JF - The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08)

ER -