Q factor damping of anti-resonance peak by variable on-die capacitance

Wataru Ichimura, Sho Kiyoshige, Masahiro Terasaki, Hiroki Otsuka, Toshio Sudo

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Power supply noise has been becoming critical in advanced CMOS digital systems, because power supply noise induces false logic operation and instability. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, Q factors of anti-resonance peaks for various PDN impedances have been examined by changing the value of on-die capacitance. As a result, it has been proved that Q factors of anti-resonance peaks can be suppressed by increasing on-die capacitance. Furthermore, power supply noise distribution on a chip has been simulated for the various location of noise generating circuits and on-die capacitance.

本文言語English
ホスト出版物のタイトルIEEE International Symposium on Electromagnetic Compatibility
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1049-1053
ページ数5
ISBN(電子版)9781479932252
DOI
出版ステータスPublished - 2014 10月 20
イベント2014 International Symposium on Electromagnetic Compatibility, EMC Europe 2014 - Gothenburg, Sweden
継続期間: 2014 9月 12014 9月 4

出版物シリーズ

名前IEEE International Symposium on Electromagnetic Compatibility
ISSN(印刷版)1077-4076
ISSN(電子版)2158-1118

Conference

Conference2014 International Symposium on Electromagnetic Compatibility, EMC Europe 2014
国/地域Sweden
CityGothenburg
Period14/9/114/9/4

ASJC Scopus subject areas

  • 凝縮系物理学
  • 電子工学および電気工学

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