Tiny Two-Stage 1-GHz Time-Difference Amplifier without Input Time-Difference Limitation and Extreme Points

Conventional time-difference amplifiers (TDAs), which can improve the time-domain resolution, use capacitors and an external control circuit to make gain, control gain, and improve linearity. However, this configuration produces a limitation in the maximum operating frequency and high power consumption. This paper proposes and demonstrates a TDA for a variety of time-domain circuits. The proposed TDA consists of two circuits, including a modified SR latch circuit and gain control circuit (GCC). The linearity of this TDA is controlled by the GCC, which is a part of the amplifier, by only using the time-difference signals generated by the modified SR latch. This TDA is fabricated in the 0.18 J.1m CMOS process, and the core area occupies only 13 µm×14 µm. The measurement results show that the output time difference monotonically increases and has no extreme points for an entire clock period with a 1-GHz input clock. The gain of the flat region in the range of ±130 ps is 1.54 with a maximum gain error of less than 6.5%, and the power consumption is 2230 µW. The proposed TDA can be used for not only a time to digital converter, similar with conventional TDAs, but also circuits using the time domain, such as a high-speed comparators and time-difference adjustment methods.